In high-speed data converters and 5G radio designs, frequency sources are often hidden bottlenecks. As data transmission rates climb and 5G moves to higher bands, performance requirements become more difficult to meet. The requirements list continues to grow and its direction often conflicts with the performance objectives.
Like the foundation of a building, everything built on the frequency source will be affected if it changes. The clock or local voltage-controlled oscillator (VCO) is that foundation, any instability of which propagates throughout the system, no matter how well the other parts are designed.
The core of each frequency synthesizer is a phase-locked loop (hereinafter referred to as PLL). PLL is the mechanism to lock the output frequency to a precise reference and hold it constant. It distinguishes a stable, controllable frequency source from a drift oscillator.
Modern applications such as radios, radars, phased arrays, multiband test equipment, and wireless infrastructure require constant hopping between different frequencies to avoid interference, support multichannel, or electronically perform beam modulation. Each time the system changes frequency, its PLL must be re-locked. Prior to this, the signal was unstable and basically unusable. The re-lock time directly affects the response speed of the entire product.
Data converters work by measuring input signals at precise, regular intervals, typically millions of times per second. The clock determines the time of each measurement. Any timing uncertainty (also known as jitter) in the clock means that the measurement occurs at the wrong time, thus introducing errors, which are shown as noise at the output. The faster the signal, the more severe the effect.
In 5G radio, the same problem occurs in different forms. The local oscillator precisely places the radio signal on the correct frequency. The phase noise in the clock source is converted into sampling jitter, which directly limits the SNR of the converter and finally affects system-level indicators such as error vector amplitude (EVM).
In both cases, the results are the same: the uncertainty of the frequency source will lead to an error that cannot be corrected downstream. The converter with excellent dynamic performance can only achieve its target performance index when the clock driving it is equally accurate.
In fact, the phase noise of the synthesizer determines how much timing uncertainty is accumulated in the clock signal (represented by RMS jitter, which is a single value representing the average size of these timing errors), and thus determines how much noise and distortion budget of the converter has been consumed before the signal is digitized.
Design considerations
When designing high-speed data converters and 5G applications, various trade-offs that may affect performance must be considered:
The phase noise determines the background noise and sets the upper limit of the dynamic range to determine the best signal resolution that can be achieved, no matter how outstanding it is in other respects. In 5G radio, it determines whether the modulation scheme can be decoded on the receiver.
The frequency range determines the flexibility. A synthesizer that can cover the target frequency band without external frequency doubling or division can simplify the design, reduce the number of components and eliminate the noise and complexity introduced by these additional cascades.
The lock time determines how quickly the system can switch channels or respond to dynamic conditions - essential in frequency hopping and beam steering applications.
PLL locks its output to a frequency by continuously comparing and correcting its output to the reference. This correction process is controlled by the feedback loop, which, like any feedback loop, requires time to stabilize because the loop must detect the error, respond and stabilize before the output can be used.
In traditional designs, loop bandwidth that determines PLL response speed also directly affects phase noise performance. Expanding the loop to speed up the lock will deteriorate the phase noise. Shrinking the loop to improve phase noise can negatively affect lock time. This fundamental trade-off means that designers must choose which is more important to their application - and bear the consequences of this choice.
The latest generation of integrated fractional N-division frequency synthesizer directly solves these trade-offs. Early solutions forced designers to choose between phase noise performance and integration, while newer devices combined ultra-low phase noise, wide frequency coverage, fast lock time, and compact packaging, integrating parts that previously required multiple discrete components into a single solution.
For the data converter clock, this means that the background noise of the frequency source is no longer a constraint on the dynamic range of the system. For 5G radio design, this means that achieving demanding error vector amplitude targets becomes a solved frequency source problem rather than a problem that must be engineered around it.- g.
Modern RF systems typically use a fractional N-division PLL synthesizer to generate a sampling clock and a local oscillator. Although these architectures allow extremely fine frequency resolution, modulation of the frequency division ratio introduces quantitative noise and fractional spurious, which affect the overall phase noise curve. The noise produced by the amplifier or filter will affect the signal, but the noise produced by the frequency source will destroy the reference, while the poor reference will destroy all modules that depend on the reference.
On-chip VCO simplifies circuit board design
Broadband frequency synthesis has traditionally meant the assembly of signal chains with discrete components (external VCO, PLL, buffers, etc.) and the consequent layout difficulties. Analog Devices, Inc. (ADI) simplifies the circuit board design by integrating VCO into a chip solution, integrating the entire signal chain into one device, and providing fast calibration capabilities for frequency hopping without sacrificing phase noise and jitter performance required for 5G radio and high-speed data converter designs.g.
Frequency switching is not done in one stroke. When PLL receives the command to switch to a new frequency, it needs to go through three different stages before the output can be changed to an available frequency. Initially, it receives a switch command. It then searches internally for the appropriate settings to produce the required frequency; This search phase is the slowest part, typically 100 to 250 microseconds in modern broadband devices. Finally, it stabilizes to ensure that the output is sufficiently clean and available.
The ADF4382 series of ADI directly solves the problem of slow intermediate links. For fast calibration, it does not need to search again each time a frequency switch is requested, but instead uses an on-chip lookup table that contains pre-calculated settings for known points in 32 frequency ranges. When a new frequency is required, it finds two nearest storage points and interpolates between them so that the correct settings are almost immediately available. In this way, the total lock time can be reduced to within 10 microseconds, with a minimum of 2 microseconds.